The present invention relates generally to semiconductor switching devices and, more particularly, to insulated gate bipolar transistors (IGBT's) optimized for zero-voltage switching (ZVS).
Presently available IGBT's are typically of two types, i.e., punch-through (PT) and non-punch-through (NPT). PT IGBT's typically use "lifetime killers" to maximize the trade-off between turn-off time and forward voltage drop. (Lifetime killers are known in the art as comprising external elements which are injected into silicon in order to reduce its lifetime.) NPT IGBT's typically use a thin P.sup.+ collector layer in order to reduce the number of charges injected into the drift layer. PT IGBT's have a buffer layer that acts as a minority carrier injection limiter and allows for a reduction in the thickness of the drift layer. Basically, the buffer layer acts as a barrier to the minority carriers and also allows the electric field in the device to stop at its edge, thereby increasing the voltage/length ratio. Hence, for a given voltage, e.g., 600 V, a PT IGBT with a buffer layer would require approximately 60-80 .mu.m of silicon to block the voltage, while an NPT IGBT without the buffer layer would require 100-120 .mu.m of silicon to block the same voltage.
Both PT and NPT IGBT's are optimized for hard-switching operation. However, ZVS (zero-voltage switching, i.e., switching with zero voltage across a device) results in significant operational advantages, particularly in converter applications, over hard-switching at high switching frequencies. Advantages include significantly reduced switching losses, higher switching frequency operation, low electromagnetic interference, lower device voltage and current stresses, better safe operating area, and low-cost thermal management system.
Accordingly, it is desirable to provide an IGBT structure which is optimized for ZVS operation and applications.